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Our Mission

To introduce simpler and more accessible methods of designing silicon by promoting the evolution and adoption of open transaction-level extensions (TL-X) for various hardware description languages (HDLs).

Computer Processor

Exponential growth in chip complexity is making chip design a very costly proposition. Standards driven by big corporate interests tend to evolve as layers upon layers, only adding to the complexity crisis.


In 2014, Intel Corporation openly released tools supporting advanced design methodology to get the community behind the vision that has become TL-X. Open-source and commercial traction have gradually followed. exists to steer the ship with the community in mind and without the direct influence of the corporate dollar.

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In TL methodology, verification is elevated to a new transaction level of abstraction. Within a TL model, logic designers are given the mechanisms to specify RTL details when necessary. We get the productivity benefits of abstraction without giving up control over the implementation.

As important as where we're going is how we get there. A chip today may have millions of lines of RTL. No one is going to rewrite them all for the next iteration. TL-X extends RTL, compiles to RTL, and works with RTL tools. New constructs and tools can displace old ones opportunistically.

What's TL-X?

Following the 35-year reign of register transfer level (RTL) modeling, transaction-level (TL) design is a vision for the next 35 years. TL-X gets us from RTL to TL without disruption.

Meet Our Steering Committee


Steve Hoover

Founder and CEO of Redwood EDA

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A veteran chip designer, Steve has been influential in the definition of TL-X from the start. As founder and CEO of Redwood EDA, LLC, Steve strives to bring commercial success to the mission.

"The silicon industry needs a major kick in the pants, and we're doing some kicking."


Theodore Omtzigt

Founder and CEO of Stillwater Supercomputing

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With deep experience in both the silicon industry and the startup community, Theo is well positioned
to enable innovative silicon design teams with the the productivity improvements that TL-X provides.

"TL-X solves one of the most time consuming and error-prone tasks in pipeline design: retiming. With TL-X this is painless, creating an immeasurable productivity improvement for high-performance silicon designs."


van der Weide

Professor at University of Wisconsin-Madison

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Dan has earned a reputation for innovating within the university setting. This includes technological innovation as well as innovation of the educational system itself.

"I'm compelled by the impact TL-X is having by exposing students to a more approachable yet universal circuit design methodology."


Kunal Ghosh

Founder of VLSI System Design

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Having reached hundreds of thousands of learners through his VLSI training programs, Kunal has helped to make TL-Verilog a recognized technology, throughout India and globally.

"It is inspirational to see the way students respond to TL-Verilog."

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